Delay-locked loop (DLL) circuits are known for generating clock signals for use locally in a larger circuit, based on a received reference or master clock. After a start-up phase in which lock is achieved, the generated signals are phase aligned with the reference signal. Conversely, Phase-locked loops (PLLs) can multiply or divide frequency by any number and provide a ‘flywheel’ effect to reduce jitter, but are correspondingly slower to lock. DLLs often have a faster locking behaviour which makes them suited for use in power-sensitive applications, where the clocks to different circuit blocks are enabled and disabled from time to time, according to need. Unlike PLLs, DLLs can be used for integer clock multiplication only (e.g. ×1, ×2, ×3 etc.) and do not attenuate the jitter on the input. However, due to the fact there are fewer thermal noise sources that in a PLL, the DLL is capable of producing a higher quality clock that a PLL. Hence their use is primarily limited to two situations:                i) a system where the input clock is of high performance and the multiplied clock must also be of high quality, such as high quality audio applications; and        ii) a system where clock multiplication is required but there is no need to attenuate the jitter on the clock, such as DSP chips.        
DLLs are based on a variable multi-stage delay line, in which the delay is controlled by a phase/frequency detector which compares the signal at the end of the delay line with the reference signal. Taps between stages in the delay line provide multiple copies of the reference signal, phase shifted so as to subdivide the clock period. These copy signals can be used individually, for example to provide a pair of clock signals in quadrature at the same frequency as the reference clock, and/or combined in a circuit to generate a frequency multiplied clock waveform. Examples of known DLL circuits can be seen in US 2004/0008063 A1 (Kim et al) and U.S. Pat. No. 6,100,736 (Wu et al).